I’ve now redrawn this board to correct the problems found with the previous version, and the new board’s schematics and layouts are now available at this link. As well as correcting the problems I had before, I’ve also managed to add in a few extra features. I’ve found two pins from each FPGA that weren’t sensibly routable, and connected one to an LED and one to a 0.1″ header for each FPGA. This helps a bit with debug, as you can more easily see what’s going on. I’ve also added the FPGA reset pin to the SPI header, which means that it’s now possible to bring up the FPGA without a Novena attached. Previously, you couldn’t do this because you couldn’t bring the FPGA out of reset without a bodge wire, but the extra pin makes it straightforward. Finally, I’ve added a 1.2V header, so you can access the FPGA core voltage if you want.

I’ve uploaded the schematics as a PDF as well as the original DipTrace and Gerber files in case anyone wants to take a look without having to download Diptrace.

The new board is, as before, under the Apache 2.0 license. I’ll be getting a few of these made up at Dirty PCBs, and will post again here when I’ve got one assembled and tested.

Also about this board:

• Part 5 – Revision 2 hardware
• Part 3 – Bitstream loader
• Part 2 – Testing revision 1 boards
• Introduction